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copyright ? cirrus logic, inc. 2012 (all rights reserved) cirrus logic, inc. http://www.cirrus.com CS1610/11 cs1612/13 triac dimmable led driver ic features & description ? best-in-class dimmer compatibility - leading-edge (triac) dimmers - trailing-edge dimmers - digital dimmers (with integrated power supply) ? up to 90% efficiency ? optimized for < 25w input power ? flicker-free dimming ? 0% minimum dimming level ? quasi-resonant second stage wi th constant-current output - flyback and buck ? fast startup ? tight led current regulation: better than 5% ? primary-side regulation (psr) ? >0.9 power factor ? iec-61000-3-2 compliant ?soft start ? protections: - output open/short - current-sense resistor open/short - external overtemperature using ntc overview the CS1610/11/12/13 is a digital control ic engineered to deliver a high-efficiency, cost-effective, flicker-free, phase-dimmable, solid-state lighting (ssl) solution for the incandescent lamp replacement market. the CS1610/11 is designed to control a quasi-resonant flyback topology. the cs1612/13 is designed to control a buck topology. the CS1610/12 and cs1611/13 are designed for 120vac and 230vac line voltage applications, respectively. the CS1610/11/12/13 integrates a critical conduction mode (crm) boost converter that provi des power factor correction and dimmer compatibility with a cons tant output current, quasi- resonant second stage. an adaptive dimmer compatibility algorithm controls the boost stage and dimmer compatibility operation mode to enable flic ker-free operation to <2% output current with leading-edge, trailing-edge, and digital dimmers (dimmers with an integrated power supply). applications & description ? dimmable retrofit led lamps ? dimmable led luminaries ? offline led drivers ? commercial lighting ordering information see page 15 . t1 d8 c9 led+ led- d7 r12 ntc z2 c8 r11 d6 r8 r13 r fb ga in q4 CS1610 /11 iac source fbgain fbaux bstout gnd sgnd 13 16 5 4 ipk clamp gd fbsense eotp 15 8 9 10 12 11 1 14 2 bstaux vdd q3 r10 3 r s c ntc r9 r ip k br1 br1 ac mains c7 l1 d2 br1 br1 d5 l2 c2 r4 r6 r7 q2 z1 c4 c3 r2 d1 r1 c1 r5 c6 d4 d3 c5 q1 r3 v rect v bst may?12 ds929f5
CS1610/11/12/13 2 ds929f5 1. introduction a typical schematic using the CS1610/11 for flyback applications is shown on the previous page. startup current is provided fr om a patent-pending, external high-voltage source-follower network. in addition to providing startup current, this unique topology is integral in providing compatibility with digital dimmers by ensuring vdd power is always available to the ic. during steady-state operation, an auxiliary winding on the boost inductor back-biases the source-follower circuit and provides steady-state operating current to the ic to improve system efficiency. the rectified input voltage is s ensed as a current into pin iac and is used to control the adaptive dimmer compatibility algorithm and extract the phase of the input voltage for output dimming control. during steady -state operation, the external high-voltage, source-follower circuit is source-switched in critical conduction mode (crm) to boost the input voltage. this allows the boost stage to maintain good power factor, provides dimmer compatibility, reduces bulk capacitor ripple current, and provides a regulated input voltage to the second stage. the output voltage of the crm boost is sensed by the current into the boost output voltage sense pin (bstout). the quasi- resonant second stage is im plemented with peak-current mode primary-side control, which eliminates the need for additional components to provide feedback from the secondary and reduces system cost and complexity. voltage across an external user -selected resistor is sensed through pin fbsense to control the peak current through the second stage inductor. leading-edge and trailing-edge blanking on pin fbsense prevents false triggering. pin fbaux is used to sense the second stage inductor demagnetization to ensure quasi-resonant switching of the output stage. when an external negative temperature coefficient (ntc) thermistor is connected to the eotp pin, the CS1610/11/12/13 monitors the system temperat ure, allowing the controller to reduce the outp ut current of the system. if the temperature reaches a design ated high set point, the ic is shutdown and stops switching. v z por + - voltage regulator 14 vdd 11 fbsense + - 15 fbaux + - 13 gd 2 iac dac + - peak contr ol second stage zcd + - output open 12 gnd olp + - 16 bstout mux ocp t leb boost zcd 3 clamp v st(th ) v stp(th) v ocp (th ) v fb zcd(th) v ovp(th ) v olp (th) v pk_max(th) 9 4 sgnd 5 source + - + - i connect v connect(th ) v source(th ) 10 fbgain 8 ipk eotp 15 k adc mux 15 k i ref t fb zcd i clamp t b s tzcd i source + - 1 bstaux v fb zcd(th ) vdd vdd figure 1. CS1610/11/12/13 block diagram
CS1610/11/12/13 ds929f5 3 2. pin description pin name pin # i/o description bstaux 1in boost zero-current detect ? boost inductor demagnetization sensing input for zero-current detection (zcd) information. the pin is connected to the pfc boost inductor auxiliary winding through an external resistor divider. iac 2in rectifier voltage sense ? a current proportional to the rectified line voltage is fed into this pin. the current is measured with an a/d converter. clamp 3out voltage clamp current source ? connect to a voltage clamp circuit on the output of the boost stage. sgnd 4pwr source ground ? common reference current return for the source pin. source 5in source switch ? connected to the source of the boost stage external high-voltage fet. nc 6in no connect ? connect this pin to vdd using a pull-up resistor. nc 7in no connect ? connect this pin to vdd using a pull-up resistor. ipk 8in boost peak current ? connect a resistor to this pin to set the peak current of the boost circuit. fbgain 9in second stage gain ? connect a resistor to this pin to set the switching frequency gain for the second stage. eotp 10 in external overtemperature protection ? connect an external ntc thermistor to this pin, allowing the internal a/d converter to sample the change to ntc resistance. fbsense 11 in second stage current sense ? the current flowing in the second stage fet is sensed across a resistor. the resulting voltage is applied to this pin and digitized for use by the second stage computational logic to de termine the fet's duty cycle. gnd 12 pwr ground ? common reference. current return fo r both the input signal portion of the ic and the gate driver. gd 13 out gate driver ? gate drive for the second stage power fet. vdd 14 pwr ic supply voltage ? connect a storage capacitor to this pin to serve as a reservoir for operating current for the device, including t he gate drive current to the power transistor . fbaux 15 in second stage zero-current detect ? second stage inductor sensing input. the pin is connected to the second stage inducto r?s auxiliary winding through an external resistor divider. bstout 16 in boost output voltage sense ? a current proportional to the boost output is fed into this pin. the current is measured with an a/d converter. no connect source switch source ground boost zero-current detect rectifier voltage sense boost peak current nc nc no connect source sgnd bstaux eotp external overtemperature protection fbsense second stage current sense gnd ground gd gate driver vdd ic supply voltage fbaux second stage zero-current detect bstout boost output voltage sense iac clamp v oltage clamp current source 16-lead soicn ipk fbgain second stage gain 7 6 5 4 3 2 1 10 11 12 13 14 15 16 8 9 figure 2. CS1610/11/12/13 pin assignments
CS1610/11/12/13 4 ds929f5 3. characteristics and specifications 3.1 electrical characteristics typical characteristics conditions: ?t a =25c, v dd =12v, gnd=0v ? all voltages are measured with respect to gnd. ? unless otherwise specified, all currents are positive when flowing into the ic. minimum/maximum characteristics conditions: ?t j = -40c to +125 c, v dd = 11v to 17v, gnd = 0 v parameter condition symbol min typ max unit vdd supply voltage operating range after turn-on v dd 11 - 17 v turn-on threshold voltage v dd increasing v st(th) -8.5-v turn-off threshold voltage (uvlo) v dd decreasing v stp(th) -7.5-v zener voltage (note 1) i dd =20ma v z 18.5 - 19.8 v vdd supply current startup supply current v dd CS1610/12 cs1611/13 v bst = 200 v v bst = 400 v i ref - - 133 133 - - ? a ? a boost maximum switching frequency f bst(max) --200khz clamp current i clamp --3.7-ma dimmer attach peak current CS1610/12 cs1611/13 108 ? v line ? 132 207 ? v line ? 253 - - 590 508 - - ma ma dcm delay in no-dimmer mode CS1610 CS1610-01 cs1611/12/13 - - - 0.0 6.4 6.4 - - - ? s ? s ? s boost zero-current detect bstzcd threshold v bstzcd(th) -200-mv bstzcd blanking t bstzcd -3.5- ? s zcd sink current (note 2) i zcd -2 - - ma bstaux upper voltage i zcd =1ma -v dd +0.6 - v boost protection boost overvoltage protection (bop) CS1610/12 cs1611/13 108 ? v line ? 132 207 ? v line ? 253 v bop(th) - - 162 148 - - ? a ? a clamp turn on CS1610/12 cs1611/13 108 ? v line ? 132 207 ? v line ? 253 - - 147 143 - - ? a ? a second stage zero-current detect fbzcd threshold v fbzcd(th) -200-mv fbzcd blanking t fbzcb -2- ? s zcd sink current (note 2) i zcd -2 - - ma fbaux upper voltage i zcd =1ma -v dd +0.6 - v
CS1610/11/12/13 ds929f5 5 notes: 1. the CS1610/11/12/13 has an internal shunt r egulator that limits the voltage on the vdd pin. v z , the shunt regulation voltage, is defined in the vdd supply voltage section on page 4 . 2. external circuitry should be designed to ensure that the zcd cu rrent drawn from the internal clamp diode when it is forward b iased does not exceed specification. 3. the conductance is specif ied in siemens (s or 1/ ? ). each lsb of the internal adc corresponds to 250ns or one parallel 4m ? resistor. full scale corresponds to 256 parallel 4m ? resistors or 15.625k ? . 4. specifications are guaranteed by desi gn and are characterized and correlated using statistical process methods. 5. for test purposes, load capacitance (c l ) is 0.25nf and is connected as shown in the following diagram. second stage current sense overcurrent protection threshold v ocp(th) -1.69-v sense resistor short threshold v olp(th) -200-mv peak control threshold v pk_max(th) -1.4-v leading-edge blanking t leb -550-ns delay to output --100ns second stage pulse width modulator minimum on time - 0.55 - ? s maximum on time - 8.8 - ? s minimum switching frequency t fb(min) -625-hz maximum switching frequency t fb(max) -200-khz second stage gate driver output source resistance v dd =12v z out -24- ? output sink resistance v dd =12v z out -11- ? rise time (note 5) c l =0.25nf --30ns fall time (note 5) c l =0.25nf --20ns second stage protection overcurrent protection (ocp) v ocp(th) -1.69-v overvoltage protection (ovp) v ovp(th) -1.25-v open loop protection (olp) v olp(th) -200-mv external overtemperature protection (eotp), boost peak current, second stage frequency gain pull-up current source ? maximum i connect -80- ? a conductance accuracy (note 3) --5 ? conductance offset (note 3) -250-ns current source voltage threshold v connect(th) -1.25-v internal overtemperature protection (iotp) thermal shutdown threshold (note 4) t sd -135-oc thermal shutdown hysteresis (note 4) t sd(hy) -14-oc parameter condition symbol min typ max unit gd out gd gnd cs vdd buffer s 1 r 1 r 2 r 3 tp c l 0. 25 nf +15v -15v s 2 v dd
CS1610/11/12/13 6 ds929f5 3.2 thermal resistance 3.3 absolute maximum ratings characteristics conditions: all voltages are measured with respect to gnd. note: 6. long-term operation at the maximum junction temperature wi ll result in reduced product life. derate internal power dissi pation at the rate of 50 mw /c for variation over temperature. warning: operation at or beyond these limits may re sult in permanent damage to the device. normal operation is not guaranteed at these extremes. symbol parameter value unit ? ja junction-to-ambient thermal impedance 2 layer pcb 4 layer pcb 84 47 c/w c/w ? jc junction-to-case thermal impedance 2 layer pcb 4 layer pcb 39 31 c/w c/w pin symbol parameter value unit 14 v dd ic supply voltage 18.5 v 1, 2, 5, 8, 9, 10,11,15,16 analog input maximum voltage -0.5 to (v dd +0.5) v 1, 2, 8, 9, 10, 11, 15, 16 analog input maximum current 5 ma 13 v gd gate drive output voltage -0.3 to (v dd +0.3) v 13 i gd gate drive output current -1.0 / +0.5 a 5i source current into pin 1.1 a 3i clamp clamp output current 5 ma -p d total power dissipation 400 mw -t j junction temperature operating range (note 6) -40 to +125 c -t stg storage temperature range -65 to +150 c all pins esd electrostatic discharge capability human body model charged device model 2000 500 v v
CS1610/11/12/13 ds929f5 7 4. typical performance plots figure 3. uvlo characteristics figure 4. supply current vs. voltage figure 5. turn on/off threshold voltage vs. temperature figure 6. zener voltage vs. temperature figure 7. gate drive resistance vs. temperature figure 8. reference current (i ref ) drift vs. temperature 0 1 2 3 -50 0 50 100 150 uvlo hysteresis temperature (oc) -2 0 2 4 6 8 0 2 4 6 8 10 12 14 16 18 20 i dd (ma) v dd (v) risin g ed g e falling edge 7 8 9 10 -50 0 50 100 150 vdd (v) temperature (oc) turn o + turn on 18 18.5 19 19.5 20 -50 0 50 100 150 v z (v) temperature (oc) 0 10 20 30 40 -50 0 50 100 150 z out ( : ) temperature (oc) sink source -2.0 -1.5 -1.0 -0.5 0.0 0.5 -50 0 50 100 150 drift (%) temperature (oc)
CS1610/11/12/13 8 ds929f5 5. general description 5.1 overview the CS1610/11/12/13 is a digital control ic engineered to deliver a high-efficiency, cost -effective, flicker-free, phase- dimmable, solid-state lighting (ssl) solution for the incandescent lamp replacement market. the CS1610/11 is designed to control a quasi-resonant flyback topology. the cs1612/13 is designed to control a buck topology. the CS1610/12 and cs1611/13 are designed for 120vac and 230vac line voltage applications, respectively. the CS1610/11/12/13 integrates a critical conduction mode (crm) boost converter that provides power factor correction and dimmer compatibility with a c onstant output current, quasi- resonant second stage. an adaptive dimmer compatibility algorithm controls the boost stage and dimmer compatibility operation mode to enable flicker-free operation to <2% output current with leading-edge, trailing-edge, and digital dimmers (dimmers with an integrated power supply). 5.2 startup circuit an external, high-voltage source-follower circuit is used to deliver startup current to the ic. during steady-state operation, an auxiliary winding on the boost inductor biases this circuit to an off state to improve system efficiency, and all ic supply current is generated from the auxiliary winding. the patent- pending technology of the external, high-voltage source- follower circuit enables system compatibility with digital dimmers (dimmers containing an internal power supply) by providing a continuous path fo r the dimmer?s power supply to recharge during its off state. du ring steady-state operation, the high-voltage fet, q2, in this circuit is source-switched by a variable internal current source on the source pin to create the boost circuit. a schottky diode with a forward voltage less than 0.6v is recommended for d5. schottky diode d5 will limit inrush current through the internal diode preventing damage to the ic. 5.3 dimmer switch detection the CS1610/11/12/13 dimmer switch detection algorithm determines if the ssl system is controlled by a regular switch, a leading-edge dimmer, or a trailing-edge dimmer. dimmer switch detection is implemented using two modes: dimmer learn mode and dimmer validate mode. these assist in limiting the system power losses. once the ic reaches its uvlo start threshold, v st(th) , and begins operating, the CS1610/11/12/13 is in dimmer learn mode, allowing the dimmer switch detection circuit to set the operating state of the ic to one of three modes: no-dimmer mode, leading-edge mode, or trailing-edge mode. 5.3.1 dimmer learn mode in dimmer learn mode, the dimmer detection circuit spends approximately two line-cycles learning whether there is a dimmer switch and, if present, whether it is a trailing-edge or leading-edge dimmer. in dimmer learn mode, a modified version of the leading-edge algorit hm is used. the trailing-side slope of the input line voltage is sensed to decide whether the dimmer switch is a trailing-edge dimmer. the dimmer detection circuit transitions to dimmer validate mode once the circuit detects a dimmer is present. 5.3.2 dimmer validate mode during normal operation, CS1610/11/12/13 is in dimmer validate mode. this instructs the dimmer detection circuit to periodically validate that the ic is executing the correct algorithm for the attached dimmer. the dimmer detection algorithm periodically verifies the ic operating state as a protection against incorrect detec tion. as additional protection, the output of the dimmer detecti on algorithm is low-pass filtered to prevent noise or transient events from changing the ic?s operating mode. the ic will return to dimmer learn mode when it has determined that the wrong algorithm is being executed. 5.3.3 no-dimmer mode upon detection that the line is not phase cut with a dimmer, the CS1610, CS1610-01, and cs1611/12/13 operates in no- dimmer mode, where it provides a power factor that is in excess of 0.9. the CS1610-01 and cs1611/12/13 accomplishes this by boosting in crm and dcm mode. the CS1610 boosts in crm mode only. the peak current is modulated to provide link regulation. the CS1610/11/12/ 13 alternates between two settings of peak current. to regulate the boost output voltage, the device uses a peak current set by the r ipk resistor. the time that this current is used is determined by an internal compensation loop to regulate the boost output voltage. the internal algorithm will reduce the peak current of the boost stage to maintain output voltage regulation and obtain the desired power factor. 5.3.4 leading-edge mode in leading-edge mode, the CS1610/11/12/13 regulates the link voltage while maintaining the dimmer phase angle. to accomplish this, the CS1610/11/12/13 uses ccm boosting with dimmer attach current as t he initial peak current on the initial firing event of the dimmer. after gaining control of the incoming current, the CS1610/11/12/13 transitions to a crm boost algorithm to regulate the link voltage. the CS1610/11/12/13 periodically exec utes a probe event on the incoming waveform. the information from the probe event is beneficial to maintaining proper operation with the dimmer circuitry. 5.3.5 trailing-edge mode in trailing-edge mode, the CS1610/11/12/13 determines its operation based on the falling edge of the input voltage waveform. to allow the dimmer to operate properly, the CS1610/11/12/13 must charge the capacitor in the dimmer on the falling edge of the input voltage. to accomplish this, the CS1610/11/12/13 always executes the boost algorithm on this falling edge. to ensure maximum compatibility with dimmer components, the device boosts during this falling edge event using a peak current that must meet a minimum value. in trailing-edge mode, only crm boosting is used.
CS1610/11/12/13 ds929f5 9 5.4 boost stage the high-voltage fet in the sour ce-follower startup circuit is source-switched by a variable current source on the source pin to operate a boost circuit. peak fet switching current is set with an external resistor on pin ipk. in no-dimmer mode, the boost stage begins operating when the start threshold is reached du ring each rectified half line-cy- cle and is disabled at the nom inal boost output voltage. the peak fet switching current determines the percentage of the rectified input voltage conduction angle over which the boost stage will operate. the control algorithm adjusts the peak fet switching current to maximize the operating time of the boost stage, thus improving the input power factor. when operating in leading-edge dimmer mode, the boost stage ensures the hold current requirement of the dimmer is met from the initiation of each half-line dimmer conduction cycle until the peak of the rectif ied input voltage. trailing-edge dimmer mode boost stage ensures that the trailing-edge is exposed at the correct time with the correct current. 5.4.1 maximum peak current the maximum boost inductor peak current is set using an external resistor, r ipk , on pin ipk, which is sampled periodically by an adc. maximu m power output is proportional to i pk(code) . see equation 1: where, ? = correction term = 0.55 v rms, typical = nominal operating input rms voltage i pk(bst) =i pk(code) x4.1ma the external resistor, r ipk , is calculated using the peak current code, i pk(code) . see equation 2: 5.4.2 output bstout sense & input iac sense a current proportional to t he boost output voltage, v bst , is supplied to the ic on pin bstout and is used as a feedback control signal. the adc is us ed to measure the magnitude of the i bstout current through resistor r bst . the magnitude of the i bstout current is then compared to an internal reference current (i ref ) of 133 ? a. figure 9. bstout input pin model resistor r bst sets the feedback current at the nominal boost output voltage. for the cs1611/13, r bst is calculated as shown in equation 3: where, v bst = nominal boost output voltage i ref = internal reference current for 120 vac line voltage applications (CS1610/12), nominal boost output voltage, v bst , is 200v, and resistor r bst is 1.5m ? . by using digital loop compensation, the voltage feedback signal does not require an external compensation network. a current proportional to the ac input voltage is supplied to the ic on pin iac and is used by the boost control algorithm. figure 10. iac input pin model resistor r iac sets the i ac current and is defined in equation 4: for optimal performance, r iac and r bst should use 1% or better resistors for best v bst voltage accuracy. 5.4.3 boost auxiliary winding the boost auxiliary winding is used for zero-current detection (zcd). the voltage on the auxiliary winding is sensed through the bstaux pin of the ic. it is also used to deliver current during steady-state operation, as mentioned in section 5.2 startup circuit on page 8. p in max , ? i pk bst ?? v rms typical , ? ?? 2 ------------------------------------------------------------------- - = [eq.1] r ipk 4000000 i pk code ?? ----------------------- = [eq.2] v bst CS1610 /11 /12 /13 15 k adc r8 r bst i bstout r9 i ref 16 bstout 12 r bst v bst i ref ------------- - 400v 133 ? a ----------------- - 3m ? ? == [eq.3] r3 r ia c i ac i ac v rect CS1610 /11 /12 /13 15 k adc r4 2 i ref 12 r iac r bst = [eq.4]
CS1610/11/12/13 10 ds929f5 5.4.4 boost overvoltage protection the CS1610/11/12/13 supports boost overvoltage protection (bop) to protect the bulk capacitor c8 (see figure 12. flyback model ). if the boost output volt age exceeds the overvoltage protection thresholds of 249v for a 120v system, or 448v for a 230v system, a bop fault signal is generated. the control logic continuously averages this bop fault signal, and if at any point in time the average exceeds a set event threshold, the boost stage is disabled. the bop fault averaging algorithm sets the event threshold such that the boost output voltage is never allowed to stay above the bop threshold for more than 1.6ms. during a boost overvoltage prot ection event, the second stage is kept enabled, and its dim input is railed to full scale. this allows the second stage to diss ipate the stored energy on the bulk capacitor (c8) quickly, bringing down the boost output voltage to a safe value. a visible flash on the led might appear, indicating that an overvoltage event has occurred. when the boost output voltage drops to 195v for a 120v application or 368v for a 230v application, the boost stage is enabled, and the syst em returns to normal operation. 5.5 voltage clamp circuit to keep dimmers conducting and prevent them from misfiring, a minimum power needs to be delivered from the dimmer to the load. this power is nominally around 2w for 230v and 120 v triac dimmers. at low dim angles (< 90), this excess power cannot be converted into light by the second output stage due to the dim mapping at light loads. the output voltage of the boost stage (v bst ) can rise above the safe operating voltage of the primary-side bulk capacitor (c6). the CS1610/11/12/13 provides active clamp circuitry on the clamp pin, as shown in figure 11. figure 11. clamp pin model a pwm control loop ensures that the voltage on v bst (the boost output) does not exceed 227 v for 120vac applications or 424 v for 230vac applications. this control turns on the bjt of the voltage clamp circuit, allowing the clamp circuit to sink current through the load resistor, preventing v bst from exceeding the maximum safe voltage. 5.5.1 clamp overpower protection the CS1610/11/12/13 clamp overpower protection (cop) control logic averages the ?on? ti me of the clamp circuit. if the output of the averaging logic exceeds 49%, a cop event is actuated, disabling the boost and second stages. the clamp circuitry is turned off during the fault event. the ?on? time averaging algorithm sets the cop threshold such that the clamp circuit cannot be cont inuously ?on? for more than 13.8ms. 5.6 dimming signal extraction and the dim mapping algorithm when operating with a dimmer, the dimming signal is extracted in the time domain and is proportional to the conduction angle of the dimmer. a control variable is passed to the quasi-resonant second stage to achieve 2% to 100% output currents. 5.7 quasi-resonant second stage the second stage is a quasi-resonant current-regulated dc- dc converter capable of flyback or buck operation, delivering the highest possible efficiency at a constant current while minimizing line frequency ripple. primary-side control is used to simplify system design and reduce system cost and complexity. figure 12. flyback model the digital algorithm ensures monotonic dimming from 2% to 100% of the dimming range wit h a linear relationship between the dimming signal and the led current. the flyback stage is controlled by sensing current in the transformer primary. clamp q3 r10 i clam p v bst s1 CS1610 /11 /12 / 13 v be vdd 3 13 11 t1 d8 c9 led + led - d7 r12 z2 c8 r11 r13 r fb ga in q4 fbgain fbaux gnd gd fbsense 15 9 12 CS1610/11 v bst
CS1610/11/12/13 ds929f5 11 a quasi-resonant buck stage is illustrated in figure 13. the buck stage is controlled by m easuring current in the buck inductor and voltage on the auxiliary winding. figure 13. buck model the digital buck algorithm ensures monotonic dimming from 2% to 100% of the dimming range with a linear relationship between the dimming signal and the led current. quasi-resonant operation is achieved by detecting second stage inductor demagnetization via an auxiliary winding. the digital control algorithm rejects line-frequency ripple created on the second stage input by the front-end boost stage, resulting in the highest possible led efficiency and long led life. 5.7.1 auxiliary winding configuration the auxiliary winding is also used for zero-current detection (zcd) and overvolt age protection (ovp). the auxiliary winding is sensed th rough the fbaux pin of the ic. 5.7.2 control parameters the second stage control parameters assure: ? line regulation ? the led current remains constant despite a 10% ac line voltage variation. ? effect of variation in transformer magnetizing inductance ? the led current remains constant over a 20% variation in magnetizing inductance. the second stage requires three inputs and generates one key output. the fbsense input is used to sense the current in the second stage inductor. when the current reaches a certain threshold, the gate drive turns off (output on pin gd). the sensed current and the fbgain input are used to determine the switching period t total . the zero-current detect input on pin fbaux is used to determine the demagnetization period t 2 . the controller then uses the time t total to determine gate turn-on time. the fbgain input is set using an external resistor, r fbgain . resistor r fbgain must be selected to ensure that the switching period t total is greater than the resonant switching period t critical at maximum output power. see equation 5: where, t critical = resonant switching period at max power t 1 = gate turn-on time t 2 = demagnetization time the switching period t total is computed for flyback topology using equation 6: where, ? = dimming factor, proportional to the duty cycle of the dimmer, between 0 and 1 i pk(fb) = transformer primary winding current fb gain =t total /t 2 ; a constant, computed at full load 13 11 r fb ga in fbgain fbaux gnd gd fbsense 15 9 12 cs1612/13 r12 r11 r13 q4 led + led - v bst c8 d8 c9 l3 t total t critical t 1 t 2 + = ?? ? [eq.5] t total i pk fb ?? t 2 ? fb gain ? ----------------- - ? ? [eq.6]
CS1610/11/12/13 12 ds929f5 for buck topology, the switching period t total is computed using equation 7: where, ? = dimming factor, proportional to the duty cycle of the dimmer, between 0 and 1 i pk(fb) = transformer primary winding current fb gain =t total /(t 1 + t 2 ); a constant, computed at full load an appropriate value for r fbgain needs to be selected to provide the correct fb gain . resistor r fbgain is calculated using the formula shown in equation 8: the value of fb gain also has a bearing on the linearity of the dimming factor versus the led current curve and must be chosen using application note an364: CS1610/11 design guide. 5.7.3 output open circuit protection output open circuit protec tion and output overvoltage protection (ovp) is implem ented by monitoring the output voltage through the transformer auxiliary winding. if the voltage on the fbaux pin exceeds a threshold (v ovp(th) ) of 1.25v, a fault condition occurs. the ic output is disabled and the controller attempts to restart after one second. 5.7.4 overcurrent protection (ocp) overcurrent protection is implemented by monitoring the voltage across the second stage s ense resistor. if this voltage exceeds a threshold (v ocp(th) ) of 1.69v, a fault condition occurs. the ic output is disabled and the controller attempts to restart after one second. 5.7.5 open loop protection (olp) both open loop protection and protection against a short of the second stage sense resistor are implemented by monitoring the voltage across the resistor. if the voltage on pin fbsense does not reach the protection threshold (v olp(th) ) of 200mv, the ic output is disabled and the controller attempts to restart after one second. 5.8 overtemperatu re protection the CS1610/11/12/13 incorporates both internal overtemper- ature protection (iotp) and the ability to connect an external overtemperature sense circuit for ic protection. typically, a ntc thermistor is used. 5.8.1 internal overtemperature protection internal overtemperature protecti on (iotp) is activated, and switching is disabled when the die temperature of the devices exceeds 135c. there is a hyst eresis of about 14c before resuming normal operation. 5.8.2 external overtemperature protection the external overtemperature protection (eotp) pin is used to implement overtemperature protection using an external negative temperature coefficien t (ntc) thermistor. the total resistance on the eotp pin is converted to an 8-bit digital ?code? (which gives an indication of the temperature) using a digital feedback loop, which adjusts the current (i connect ) into the ntc and series resistor (r s ) to maintain a constant reference voltage of 1.25v (v connect(th) ). figure 14 illustrates the functional block diagram when connecting an optional external ntc temperature sensor to the eotp circuit. figure 14. eotp functional diagram current i connect is generated from an 8-bit controlled current source with a full-scale current of 80 ? a. see equation 9: when the loop is in equilibrium, the voltage on the eotp pin fluctuates around v connect(th) . the digital ?code? output by the adc is used to generate i connect . in normal operating mode, the i connect current is updated once every seventh half line-cycle by a single lsb step. see equation 10: solving equation 10 for code: the tracking range of this resistance adc is approximately 15.5k ? to 4m ? . the series resistor r s is used to adjust the resistance of the ntc to fall with in this adc tracking range so that the entire 8-bit dynamic range of the adc is well used. a 14k ? (1% tolerance) series resistor is required to allow measurements of up to 130c to be within the eotp tracking range when a 100k ? ntc with a beta of 4334 is used. the eotp tracking circuit is desi gned to function accurately with external capacitance up to 470pf. a higher 8-bit code output reflects a lower resistance and hence a higher external temperature. t total i pk fb ?? t 1 t 2 + ?? ? fb gain ? ----------------- - ? ? [eq.7] r fbgain 6250 fb gain 2 ? ?? 1 ? ----------------------------------------- - = [eq.8] CS1610/11/12/13 + - i connect v connect (th) comp_out eotp control eotp r s c ntc ntc v dd 10 (optional ) i connect v connect th ?? r ------------------------------------- = [eq.9] code i connect 2 n -------------------------- - ? v connect th ?? r ntc r s + ------------------------------------- = [eq.10] code 2 n v connect th ?? ? i connect r ntc r s + ?? ? ------------------------------------------------------------------ - = 256 1.25 v ? 80 ? a ?? r ntc r s + ?? ? ----------------------------------------------------------- = 410 6 ? r ntc r s + ?? --------------------------------- = [eq.11]
CS1610/11/12/13 ds929f5 13 the adc output code is filtered to suppress noise and compared against a reference code that corresponds to 125/130c. if the temperature exceeds this threshold, the chip enters an external ov ertemperature state and shuts down. this is not a latched protection state, and the adc keeps tracking the temperature in this state in order to clear the fault state once the temperature drops below 110c. when exiting reset, the chip enters startup and the adc quickly (<5ms) tracks the external temperature to check if it is below the 110c reference code before the boost and second stages are powered up. if this check fails, the chip will wait until this condition becomes true before initializing the rest of the system. for external overtemperature protection, a second low-pass filter with a time constant of two minutes filters the adc output and uses it to scale down the internal dim level of the system (and hence the led current, i led ) if the temperature exceeds 95 c (see figure 15). the large time constant for this filter ensures that the dim scaling does not happen spontaneously and is not noticeable (suppress spurious glitches). the i led starts reducing when r ntc ~ 6.3k ? (assuming a 14k ???? 1% tolerance, series resisto r), which corresponds to a temperature of 95c for a 100k ? ntc (100k ? at 25c). the i led current is scaled until the ntc value reaches 2.5k ? (125c). the CS1610/11/12/13 uses this calculated value to scale the output led current, i led , as shown in figure 15. figure 15. led current vs. eotp temperature beyond this temperature, the ic shuts down using the mechanism discussed above. if the external overtemperature protection feature is not re quired, connect the eotp pin to gnd using a 50k ? -to-500k ? resistor to disable the eotp feature. temperature ( c ) current (i led , nom.) 125 95 50% 100% 0 25
CS1610/11/12/13 14 ds929f5 6. package drawing 1. controlling dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m. 3. this drawing conforms to jedec outline ms-012, variation ac for standard 16 soicn narrow body. 4. recommended reflow profile is per jedec/ipc j-std-020. mm inch dimension min nom max min nom max a -- -- 1.75 -- -- 0.069 a1 0.10 -- 0.25 0.004 -- 0.010 b 0.31 -- 0.51 0.012 -- 0.020 c 0.10 -- 0.25 0.004 -- 0.010 d 9.90bsc 0.390bsc d1 4.95 5.10 5.25 0.195 0.201 0.207 e 6.00bsc 0.236bsc e1 3.90bsc 0.154bsc e2 2.35 2.50 2.65 0.093 0.098 0.104 e 1.27bsc 0.05bsc l 0.40 -- 1.27 0.016 -- 0.050 0 -- 8 0 -- 8 aaa 0.10 0.004 bbb 0.25 0.010 ddd 0.25 0.010 16 soicn (150 mil body with exposed pad)
CS1610/11/12/13 ds929f5 15 7. ordering information 8. environmental, manufacturing , & handling information ordering number ac line voltage temperature range package description CS1610-fsz 120vac -40 c to +125 c 16-lead soicn, lead (pb) free CS161001-fsz 120vac -40 c to +125 c 16-lead soicn, lead (pb) free cs1611-fsz 230vac -40 c to +125 c 16-lead soicn, lead (pb) free cs1612-fsz 120vac -40 c to +125 c 16-lead soicn, lead (pb) free cs1613-fsz 230vac -40 c to +125 c 16-lead soicn, lead (pb) free part number peak reflow temp msl rating a a. msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. max floor life b b. stored at 30c, 60% relative humidity. CS1610-fsz 260c 3 7 days CS1610-01-fsz 260c 3 7 days cs1611-fsz 260c 3 7 days cs1612-fsz 260c 3 7 days cs1613-fsz 260c 3 7 days
CS1610/11/12/13 16 ds929f5 revision history revision date changes pp1 mar 2011 added second stage gain section. preliminary status. pp2 may 2011 added cs1611 230v device. pp3 oct 2011 moved power supply to boost auxiliary winding. pp4 nov 2011 added cs1612/13. edited for content and clarity. f1 dec 2011 edited for clarity and typographical error. f2 feb 2012 corrected typographical errors. f3 mar 2012 edited for content and clarity. f4 apr 2012 removed ambient temperature range specification, increased power dissipation specification. corrected typographical errors. f5 may 2012 added CS1610-01 specification to the boost section in the charac- teristics and specifications table and ordering information section. updated CS1610 dcm value.
CS1610/11/12/13 ds929f5 17 contacting cirrus logic support for all product questions and inqui ries contact a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). ci rrus products are not designed, au thorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life support products or other crit- ical applications. inclusio n of cirrus products in such appl ications is understood to be fully at the customer's risk and cir- rus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is us ed in such a manner. if the customer or custom- er's customer uses or permits the use of cirrus products in critical appl ications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including at- torneys' fees and costs, that may result fr om or arise in connec tion with these uses. cirrus logic, cirrus, the cirrus logic logo designs, exl core, the exl core logo design, trudim, and the trudim logo design are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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